The present invention relates to semiconductor devices, and more specifically, to fabrication methods and resulting structures for a vertical transistor having dual bottom spacers.
As demands to reduce the dimensions of transistor devices continue, new designs and fabrication techniques to achieve a reduced device footprint are developed. Vertical-type transistors such as vertical field effect transistors (vertical FETs) have recently been developed to achieve a reduced FET device footprint without comprising necessary FET device performance characteristics. When forming these vertical FETS, spacers need to be provided between and around vertical structures.
The formation of such spacers can be problematic, however, especially in the case of bottom spacers that run along upper substrate surfaces. Indeed, bottom spacer formation often requires that a directional deposition process be executed and, while directional deposition processing is possible, this type of processing often requires additional treatments aimed at removing deposited materials from fin sidewalls. In other cases, directional deposition processing leads to loading effects that can be problematic for tight-pitch structures in aggressively scaled devices.